`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
*                                                                             *
* Copyright (c) 2012 Andrew D. Zonenberg                                      *
* All rights reserved.                                                        *
*                                                                             *
* Redistribution and use in source and binary forms, with or without modifi-  *
* cation, are permitted provided that the following conditions are met:       *
*                                                                             *
*    * Redistributions of source code must retain the above copyright notice  *
*      this list of conditions and the following disclaimer.                  *
*                                                                             *
*    * Redistributions in binary form must reproduce the above copyright      *
*      notice, this list of conditions and the following disclaimer in the    *
*      documentation and/or other materials provided with the distribution.   *
*                                                                             *
*    * Neither the name of the author nor the names of any contributors may be*
*      used to endorse or promote products derived from this software without *
*      specific prior written permission.                                     *
*                                                                             *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED *
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF        *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN     *
* NO EVENT SHALL THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT,         *
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT    *
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,   *
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY       *
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT         *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF    *
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.           *
*                                                                             *
******************************************************************************/

/**
	@file UticaCPUCoprocessor0.v
	@author Andrew D. Zonenberg
	@brief Coprocessor 0
 */
module UticaCPUCoprocessor0(
	clk,
	w_enable,	w_regid,	w_data,
					r_regid,	r_data
    );

	///////////////////////////////////////////////////////////////////////////////////////////////
	// IO declarations
	input wire clk;

	input wire w_enable;
	input wire[4:0] w_regid;
	input wire[31:0] w_data;

	input wire[4:0] r_regid;
	output reg[31:0] r_data = 0;
	
	localparam REG_COUNT = 9;

	///////////////////////////////////////////////////////////////////////////////////////////////
	// Internal stuff and read logic
	reg[32:0] count_reg = 0;	//32:1 count at Fclk/2 as per MIPS spec
	always @(posedge clk) begin
		count_reg <= count_reg + 32'h1;
		
		if(w_enable && w_regid == REG_COUNT)
			count_reg <= {w_data, 1'b1};
	end
	 
	///////////////////////////////////////////////////////////////////////////////////////////////
	// Read logic
	always @(posedge clk) begin
		
		//Read stuff
		case(r_regid)
			REG_COUNT:	r_data <= count_reg[32:1];
			default:		r_data <= 32'h0;			//unknown reg
		endcase
		
	end

endmodule
